Reducing Energy Consumption of Ip--ops

Flip-ops are one of the most power-consuming components of digital circuits. Even when there is no activity at their inputs, the mere triggering of the clock produces a signiicant waste of energy. This paper presents some techniques to reduce power consumption by selectively deactivating the clock when ip-ops do not have to change their value. Several ip-op structures are proposed and criteria are given to select among them to obtain the minimum energy consumption. These novel structures may impose some timing constraints on the pulse widths of the clock. These constraints are analyzed and their innuence on the circuit's performance evaluated. In some applications where the next state of the ip-op depends on the present value (such as accumulators), the use of selective activation might result in a simpliication of the combinational network, resulting in additional energy savings. By combining these techniques with novel coding approaches for redundant representations, tangible improvements can also be achieved for some arithmetic circuits, such as multipliers and accumulators. Experimental results have shown signiicant power savings.